The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Application No. 2000-61265 filed on Oct. 18, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a method for inspecting electrical properties of a wafer and an apparatus therefor, more particularly to a method for inspecting electrical properties of a wafer by using a probe station having a probe card and a performance board installed therein and an apparatus for inspecting the electrical properties of the wafer.
2. Description of the Related Art
Currently, due to widespread usage of computers in information media, developments in semiconductor memory devices are advancing at a rapid pace, to provide semiconductor devices having high memory storage capacity and faster operating speed. To this end, the current technology is focused on developing and realizing memory devices having a high degree of integration, response speed, and reliability.
A semiconductor device generally may be manufactured by using a wafer composed of silicon (Si). In general, the manufacturing technology of semiconductor devices includes a fabrication process and an assembly process. In the fabrication process, a structure having integrated circuits is manufactured by repeatedly forming predetermined patterns on a wafer. Also, in the assembly process, the wafer having the structure thereon is cut into chip units, and then the chips are packaged. An electrical die sorting (EDS) process is carried out between the fabrication and the assembly processes, so as to inspect electrical properties of the structure formed on the wafer.
During the electric die sorting process, the structure on the wafer is inspected to determine whether the structure has good or bad electrical properties. A structure having bad electrical properties is removed during the electric die sorting process before the assembly process is performed, so that manufacturing effort and cost may be reduced during the assembly process and so that a structure having bad electric qualities is detected early and repaired.
Electric die sorting processes for inspecting electrical properties of a wafer are disclosed in Japanese Patent Laid Open Publication No. Hei 6-181248, Japanese Patent Laid Open Publication No. Hei 10-150082, U.S. Pat. No. 5,254,939 (issued to Anderson et al.), U.S. Pat. No. 5,506,498 (issued to Anderson et al.) and U.S. Pat. No. 5,886,024 (issued to De Villeneuve).
In electric die sorting processes for inspecting the electrical properties of a wafer, the electrical properties of a structure on the wafer are inspected by a probe station having a probe card and a performance board therein. Then, a tester verifies the inspection result from the electric die sorting processes for inspecting the electrical properties of the wafer. In this case, the structure on the wafer may be a 64 mega bit direct random access memory (DRAM) or a 256 mega bit DRAM, for example. Hence, elements such as the probe card and the performance board of the probe station should be suitably installed according to the structure to be inspected.
However, the probe card and the performance board have a construction such that a user manually installs the probe card and the performance board in the probe station in accordance with the inspection process, so that the probe card and the performance board frequently do not correctly match the structure on the wafer.
To overcome such a problem, elements such as the probe card and the performance board are automatically installed by using a computer, as in U.S. Pat. No. 5,254,939. Also, in U.S. Pat. No. 5,506,498, information members are formed on the probe card, and the information members include information identifying that the probe card inspects predetermined sorts of wafers. Furthermore, Japanese Patent Laid Open Publication No. Hei 10-150082 presents discrimination numbers endowed to the probe card and the performance board, which identify the type of the probe card and the performance board. Therefore, a probe card and a performance board that are suitable to a structure having an integrated circuit (IC) formed on a wafer, are installed in the probe station by utilizing the information members or the discrimination numbers.
Although a probe card and a performance board suitable to the structure may be installed in the probe station by using the information members or the discrimination numbers, the inspection process is however continuously disturbed due to various installations of the probe card and the performance board. This is because the probe card and the performance board are not verified as to whether or not they respectively match a probe card and a performance board required to inspect identical sorts of wafers from among some wafers to be inspected during the inspection process. That is, the information member or the discrimination numbers can be respectively verified for a probe card and performance board. However, the information member or the discrimination numbers cannot be used to decide whether a probe card and a performance board respectively match a probe card and a performance board for inspecting identical sorts of wafers.
For example, when a wafer having a structure such as a 64 mega bit DRAM is inspected, the probe card and the performance board should be suitable for the structure of the 64 mega bit DRAM. Hence, the probe card and the performance board are installed after the probe card and the performance board are sufficiently verified. However, it is difficult to verify one of the probe card and the performance board when the probe card for inspecting a 256 mega bit DRAM or the performance board for inspecting a 256 mega bit DRAM are already installed.
Therefore, an inferior inspection process frequently occurs and the manufacturing reliability of the semiconductor device is reduced, because information about the probe card cannot be compared with information about the performance board, even though the probe card and the performance board should be verified by using the information members or the discrimination numbers.
The present invention is therefore directed to a method for inspecting electrical properties of a wafer and an apparatus therefor, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
It is therefore a first objective of the present invention to provide a method for inspecting electrical properties of a wafer, which enables verification of a probe card and a performance board in a probe station for inspecting identical sorts of wafers, by providing information members for the probe card and the performance board and by comparing the information members.
It is a second objective of the present invention to provide an apparatus for inspecting electrical properties of a wafer, which enables verification of a probe card and a performance board in a probe station for inspecting identical sorts of wafers, by providing information members for the probe card and the performance board and by comparing the information members.
To accomplish the first objective of the present invention, an embodiment of the present invention provides a method for inspecting electrical properties of a wafer. A probe card and a performance board are installed in a probe station for inspecting electrical properties of wafers, wherein the probe card makes contact with the wafers to transfer an electric signal and to receive an electric signal, and the performance board transfers and receives the electric signal through the probe card. Whether the probe card and the performance board respectively correspond to a probe card and a performance board usable to respectively inspect predetermined sorts of wafers among the wafers is verified. Then, a previously input inspecting information corresponding to an inspection is read out by utilizing the probe card and the performance board, when the probe card and the performance board respectively match the probe card and the performance board usable to inspect identical wafers among the wafers, after comparing a verified result concerning the probe card with a verified result concerning the performance board. The probe card and the performance board are set to an installation condition for inspecting on the basis of the inspection information, and a wafer to be inspected is placed on a chuck of the probe station. The electric signal is transferred to the wafer and an electric signal is received from the wafer through the probe card and the performance board, and electrical properties of the wafer are analyzed based on the electric signal.
The probe card and the performance board may be verified by reading integrated circuit chips respectively installed in the probe card and the performance board, or by reading bar codes respectively installed on the probe card and the performance board.
The inspection information comprises information regarding a size of a wafer for inspection, information regarding a position of a flat zone of a wafer or information regarding sizes of chips formed on a wafer. Such information becomes installation information standards for installing the probe card and the performance board in order to inspect the wafer.
The setting of the probe card and the performance board proceed by comparing installation conditions of the probe card and the performance board with installation conditions according to the inspection information and by manually proceeding according to the result generated from the comparing step. Also, the setting of the probe card and the performance board proceed by comparing installation conditions of the probe card and the performance board with installation conditions according to the inspection information and by automatically proceeding according to the result generated from the comparing step. The setting step including the arrangements of the probe card and the performance board is performed since the probe card and the performance board are manually installed in the installing.
The information read from the probe card and the performance board is compared, so the inspection process is prevented from proceeding when the probe card and the performance board have different constructions with respect to each other. Also, the information of the probe card and the performance board are previously verified so that the installation conditions of the probe card and the performance board are automatically set for inspecting. Therefore, electrical properties of the wafer can be accurately inspected.
Also, to accomplish the second objective of the present invention, one preferred embodiment of the present invention provides an apparatus for inspecting electrical properties of a wafer, including a probe station for installing a probe card for contacting with wafers to transfer an electric signal and to receive an electric signal, and a performance board for transferring and receiving the electric signal through the probe card, wherein information members are respectively provided to the probe card and the performance board, the information members including information identifying that the probe card and the performance board are respectively for inspecting predetermined sorts of wafers among the wafers. A reader reads the information members and a controller sets the probe card and the performance board to installation conditions for inspection in view of inspection information, wherein the controller reads previously input inspection information corresponding to an inspection by using the probe card and the performance board, when the probe card and the performance board respectively correspond to a probe card and a performance board which inspect identical sorts of wafers, after the controller receives information generated from the reader and compares information about the probe card with information about the performance board.
The information members may be integrated circuit chips installed in the probe card and the performance board, respectively. Also, the information members may include bar codes attached to the probe card and the performance board, respectively.
The controller has a monitor for monitoring installation conditions of the probe card and the performance board and installation conditions according to the inspection information, and an operator for manually manipulating the installation conditions of the probe card and the performance board by monitoring of the monitor. Also, the controller further includes a comparer for comparing installation conditions of the probe card and the performance board with installation conditions of the inspection information, and an automatic controller for setting installation conditions of the probe card and the performance board with automatic control based on data, after the automatic controller receives the data generated from the comparer. The automatic controller sets installation conditions of the probe card and the performance board with automatic control according to numerical control.
According to the present invention, inferiority due to incorrect installation of the probe card and the performance board can be minimized, because of inspecting whether or not the probe card and the performance board installed in the probe station are usable to inspect identical sorts of wafers. Then, successive processes are carried out on the basis of the result from the decision, so inspection reliability for semiconductor devices can be enhanced. Also, the desired time for inspecting the semiconductor devices can be reduced because of easy setting of the probe card and the performance board based on of the inspection information according to the result. Therefore, productive use of the semiconductor devices can be increased due to the inspection of the semiconductor devices.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.